A flexible and scalable architecture for a multichannel fast Fourier transform (FFT) processor, to be implemented on field-programmable gate arrays (FPGAs), is proposed in this paper. The main purpose is to evaluate the feasibility of a design that uses multiple FFT intellectual properties (IPs) to process small portions of a larger signal. Additionally, this work aims to explore the parallelism and high-speed processing intrinsic to an FPGA in the context of electronic warfare applications. Therefore, this study intends to provide a solution capable of straightly interact with the high throughput originated by radio frequency front-ends, and quickly supply frequency domain information of the incoming signals to the detection and estimation units. The proposed architecture was implemented and tested on a Zybo Z7-20 development board. The experiments show that the parallel bank of FFT IPs is realizable and in fact delivers higher performance when compared to a software-based implementation.
